Beginner Physical Design using Open-Source EDA Tools

About Workshop

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

• Students will be able to build and configure their own SoC (System-On Chip)
• Students will be able to create their own defition of GPIO
• Understand decision making process like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more

About Industry Expert: Mr. Kunal P Ghosh

Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010.

He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

The workshop is open to all VLSI aspirants including Students, Professionals, Faculty and Research Scholars

Workshop Structure

• Commencement Date: Wednesday, March 03, 2021
• No. of Learning Tracks: 5
• Schedule: Every Day from date of commencement (5 Days)
• Doubt Solving Session: 06:00 PM to 07:30 PM IST
• Program Time: 120 Hours
• Cloud-based dedicated Virtual Machine to perform Design labs

Program Fee (incl Tax) per Candidate

Learning Tracks

Track 1 - To study various components of RISC-V microprocessor based SoC and review RISC-V picoSoC

• Brief introduction RISC-V ISA and simulator. Run simple calculator ‘C’ code on a real processor written in Verilog
• Overview of RISC-V based micro-processor and its related SoC
• Overview of QFN48 package, pads, macros, analog components, and memory in open-source
• Mixed-signal functionality simulation and Logic synthesis of above picoSoC verilog using open-source Synthesis engine

Track 2 - To understand importance of good vs bad floorplan and introduction to library cells using open- source tool

• Pros and cons of good-bad floorplan
• Idea of chip-planning, aspect ratio, utilization factor, power planning, decoupling capacitor, pads/memory, and macro placement
• Introduction to lab to create floorplan for small design, which will be covered in detail on Day 4)
• Physical design overview
• Why Libraries are called the soul and heart of semi-conductor industry?
• Standard cells library overview

Track 3 - To design and characterize one library cell using open-source Layout tool and spice simulator

• Art of layout – Stick diagram + Euler’s path using open-source Layout tools
• Characterization of important parameters (rise_time, rise_delay, fall_time, fall_delay) using open-source SPICE tool
• Introduction to 16-Mask CMOS fabrication process and its significance to chip design flow
• High fanout net synthesis interactive tutorial using open-source synthesis too

Track 4 - To do pre-layout static timing analysis and understand the importance of good clock tree

• Introduction to static timing analysis and the related Industry standard reporting formats
• Pre-layout timing analysis of a design using open-source STA tool, which includes setup timing analysis for reg2reg and IO
• Introduction to clock tree synthesis (CTS) and its related checks viz. skew, latency, pulse-width, duty cycle
• Placement/Routing/CTS of a design using open-source RTL2GDS tool
• Perform CTS quality and routing quality checks using open-source STA

Track 5 - To understand full-chip integration steps and implement E31 RISCV design using open-source tool- chain

• Full chip integration using open-source for a design with blocks and pads.
• Revise floorplan from Day 2
• Populate layout from library manager in open-source, select digital core block and additional pads
• Arrange pads and create a pad-frame hierarchy
• Project work using SiFive E31 RISC-V design blocks

Delivery Mode

• Virtual Coach platform with expert instructor guidance
• Cloud-based dedicated Virtual Machine to perform Design labs
• Intelligent Assessment Technology (IAT) and Project allocation
• 24 hours Lab access for 5 days and Instructor assistance on demand
• Run EDA scripts, evaluate VLSI layout and Timing analysis reports on platform.

Frequently Asked Questions

Q1. Is this workshop online or offline?

The whole journey of Silicon Proven Training is online and candidates will be trained under guidance of experts along with access to cloud based labs for practice.

Q2. How much is the fee?

The regular workshop fee is Rs 5,250 and under Early Bird Benefits,candidates can avail Rs 300 off on this fee. Also, if there is a bulk enrolment of 10 candidates and above, then candidates can have Rs 500 off on this fee.

Q3. Is this fee for the whole journey i.e. 2 workshops and 8 weeks internship?

Every workshop and internship is charged separately.

Q4. Who will take the workshop? Will Kunal only take or there are other industry experts under them?

Kunal Ghosh will conduct this workshop and candidates will get under his guidance. We request you to check delivery mode on the workshop page.

Q5. Is this the first batch of VLSI Workshop?

On 13x, it is the first workshop. This workshop we are conducting in partnership with VLSI System Design and they already trained 500+ candidates on this.

Q6. What all things will be covered in this workshop?

Request you to refer to the 5 learning tracks of this workshop given on the link. We have furnished all details of training which will be covered in 5 days and also the delivery mode.

Q7. What all technologies will be used in this workshop?

• Google/Skywater 130nm technology
• OpenLANE RTL2GDS tool chain which uses Yosys for Synthesis
• OpenRoad for PNR
• ngspice for Spice simulations
• Magic for Layout
• OpenSTA for timing analysis

Q8. The fee is very high, can you help with more discounts?

You can make use of a bulk enrolment discount which will give you Rs 500 off. You can do this by consulting your institution or creating a group of students to join.

Q9. Why is the fee high?

The fee is being charged to give you a virtual environment to practice and train you. The delivery mode of this workshop

• Virtual Coach platform with expert instructor guidance
• Cloud-based dedicated Virtual Machine to perform Design labs
• Intelligent Assessment Technology (IAT) and Project allocation
• 24 hours Lab access for 5 days and Instructor assistance on demand
• Run EDA scripts, evaluate VLSI layout and Timing analysis reports on platform.

Q10. When is the internship starting? Can we join an internship directly?

8 Weeks Internship will start after completion of 2 Workshops. To be eligible for internship, one has to undergo Beginner and Advanced Level Workshop and qualify assessment.